This invention is applicable to a shared memory controller in a multiprocessor system. The multiprocessor system is divided into per-CPU and per-memory bank logic blocks. Each per-CPU logic contains prefetch buffers with one entry corresponding to each bank of memory that can be accessed. The prefetch buffers are filled speculatively based on the last access made by the CPU. On an access from the master matching the address of an entry in the prefetch buffer known as a hit, the prefetched data is supplied to the CPU. On an access from the master having an address within a memory bank of prefetched data but not the address of the prefetched data, the contents of that entry are invalidated and a prefetch request issued from the per-CPU logic to the per-bank logic. Prefetch requests in the per-bank logic compete with real read accesses, write accesses and prefetch requests from other per-CPU logic. A prefetch request has the lowest priority. Thus a prefetch request may take a long time to complete. While the prefetch request is waiting in the per-bank logic for service, the master of the per-CPU logic that initiated the prefetch request may issue a real request to the same bank.
If the real request is to the same address as the prefetch request, there are 2 possible options. The real request can be ignored. In this alternative, the data returned by the prefetch request is sent to the requesting master. Since the prefetch request has the lowest priority, the prefetch access may take longer than if the new real request had been sent to the per-bank logic. The second alternative terminates the prefetch request and sends the new real request to the per-memory bank logic. This does not take advantage of the case where the prefetch request is complete and the data in available. The new real access request will incur additional delay going through arbitration again.